GCC Patches Added -mcpu=native -mtune=native Support For RISC-V

A SiFive engineer posted patches today for the GNU Compiler Collection (GCC) for adding -mtune=native -mcpu=native support for the compiler on RISC-V.

Kito Cheng of SiFive posted the patches for wiring up "-mcpu=native -mtune=native" RISC-V GCC support so it aligns with other architectures in supporting these options for tuning and catering the ISA to the CPU core in use for the local system. It's unfortunate it has taken so long for these "native" CPU/tuning options to come but at least now it's on approach and will hopefully be merged ahead of next year's GCC 17 compiler release.

This patch series contains the GCC RISC-V -mcpu=native and -mtune=native support. One caveat to the RISC-V support is that it doesn't yet have support for RISC-V hybrid / asymmetric CPU core designs. The patches also improve GCC's identification for the SiFive P550 / P870-D / U74 and Spacemit X60 / X100 / A100 cores.