LLVM Improves Zen 1 / Zen 2 Support To Deal With "Notoriously Bad" PDEP/PEXT

The LLVM/Clang compiler toolchain merged overnight better support for the nearly decade-old AMD Zen 1 processors and also helps with Zen+ and Zen 2 processors too. This latest work thanks to the open-source community is for providing more informed instruction scheduling around PDEP and PEXT that end up being quite costly for these original Zen processors.

Compiler engineer Simon Pilgrim took to improving the PDEP and PEXT scalar instruction scheduling for Zen 1 / Zen+ / Zen 2 processors due to their "notoriously bad" implementations. Both instructions are part of the bit manipulation BMI2 extension with PEXT being for Parallel Bits Extract and PDEP for Parallel Bits Deposit. These instructions can be used in databases, cryptography, and for games like chess and Sudoku.

Due to LLVM preparing to begin generating PDEP/PEXT intrinsics, Simon took to improving the PDEP/PEXT instruction scheduling for these old AMD Ryzen and EPYC processors based on profiling their high cost so the instruction scheduler for the znver1/znver2 targeting can make more informed choices.

"znver1/znver2 have notoriously bad implementations of the PDEP/PEXT scalar instructions, just using the WriteMicrocoded tag isn't useful as it can't give any indication of the awful effect on ALU pipes or uops flooding (especially for the rm fold variants).

The measurements on uops.info/Agner are all over the place (and are very input dependent), so I've taken an average of the worse case to at least give the scheduler something to work with.

We've ignored these so far, but now we're close to generating llvm.pdep/pext intrinsics (and scalarizing vector implementations)."

The code is now merged to LLVM Git for those looking to make the most of znver1/znver2 compiler optimizations.